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na vigator ? motion pr ocessor MC2400 series t e chnical specifications f o r micr ostepping motion c ont r o l perform a n ce m o ti on de vic e s , in c. 55 old b e dfor d r oad lincol n, ma 0 177 3 revisi on 1.7, february 20 0 4
notice this docu me nt c o n t ai ns pr opri e ta ry a n d con f iden tial in form ati on of perfor ma nc e m o tio n devi c e s, inc., a n d is pr ote c ted by fed e ral c o p y righ t law. th e c o ntents of this document may not be disclose d to t h ird pa rtie s, transl a t e d, copied, or dupl icat ed in an y f o rm, in wh ole or in p a rt, wi t hout the expr ess writt e n p e rmi ssion of pm d . th e inf o rm ati on c o n t ai ned i n this do cume nt is subjec t t o ch ang e wit h out n o tic e . n o pa rt o f this docume nt m a y be re pr oduced or tra n smi t ted in a n y f o r m , by a n y me ans, el ectr o nic or mec h a n ic a l , for a n y pur p o s e, with out t h e expr ess writ ten per m issio n of pm d. copyright 199 8, 1999 by performance motion devices, i n c. navigat o r and c-motion a r e trade m arks of perf orm a n ce m o ti on de vices, inc
wa r r a n t y pm d warr ant s perfo r ma nc e of its pr oduct s to th e spe c if icati ons a p p lic able at t h e tim e of sale i n acc o rda n ce wi th pm d ' s sta n dard warr an t y . testi n g a n d othe r qualit y co ntr o l te ch niques are util ized to t h e ex te nt pm d deems nec e ssary to s u ppo rt t h is w a rra nt y. spe c if ic testi n g of al l para m e t ers o f eac h device is no t ne cessaril y perf orm e d, exce pt t hos e mand ated b y gover n me nt r e quireme nts. perfor ma nc e m o tio n devi c e s, inc. (pm d ) reserves th e right to make changes to its products or to disconti n ue a n y pr oduct or service wit h o u t no tice, and advises custo m ers t o ob tai n th e lat e st ve rsion of relev a n t inf o rm atio n t o v e rify, b e f o re p l acing orders, tha t inf o rm ati on b e ing r e lie d on is curren t and co mpl e te . all products are sold subje c t t o th e te rm s and co nditio ns of sale sup p lied at the ti me of order ack n owledge m en t, including t h o s e per t ai ning t o warr an ty, pa ten t infri n ge m e nt, and limitation of li ability. safety notice certain applications using s e mic onductor products may involve pote ntial risks of death, pers onal injury, or sev e re pr ope rty or enviro nm en t a l damag e . pr oducts are no t designed, aut hori z ed, or warra nt ed to be suita b le f o r use in life supp o r t devices or syst ems or ot h e r crit ica l app licat ion s . inclusion of p m d products in such a ppli c atio ns is understood to be fully at the cus t omer's risk. in order to mi nimize risks associated with the cust om er's appli c ati o ns, adequate desi gn and operati ng safeguards mu st be p r ovided by t h e cust o m er t o mini mi ze in here nt pr ocedural haz a r ds. disclaimer pmd assumes no liability for applic ati o ns assistance or custom er product design. pmd does not warra nt or re p r esen t t hat an y licens e , eit h e r express or implied, is gra n ted under an y pa te nt rig h t, copyrig h t, m a sk work right, or other i n tellectual pr op erty righ t o f pm d co verin g or rela t i n g to any com b in ati on, mac h in e, or p r ocess in whic h such pr oduc ts or servic es might be o r ar e used. pm d's public ati on of infor m ati o n r e garding an y t h ird par ty 's pr oducts or serv ices does n o t cons titut e pm d's ap prov al, war r an ty or endo r s emen t t h er eo f. MC2400 t e chni cal specifi cati ons iii
MC2400 t e chni cal specifi cati ons iv
related documents navigator m o tion processor user? s guide (mc200 0ug) how t o set u p and use all m e mb ers of t h e naviga tor m o ti on pr ocess o r fa mily. navigator m o tion processor progra mmer?s refere nce (mc2000pr) descri pti ons of all n a viga t o r m o ti on pr ocess o r co m m ands, wit h c o ding syn t ax a n d exam ples, listed alphabetically for quick reference. navigat o r m o tion proces so r technical specifications five bo okle ts con t ai ning ph ysical a n d elec trical ch ara c te ristics, timi ng diagrams, pin o uts, a n d pin descripti ons o f eac h series: mc2100 series, for brushed servo motion control (mc2 100ts); mc2300 series, for brushles s servo motion control (mc2300ts); MC2400 series, for microstepping motion control (MC2400ts); mc2500 series, for ste pping motion control (mc2500ts); mc2800 series, for brushed servo and brus hless servo motion control (mc2800ts). navigator m o tion processor develope r?s kit manual (dk2000 m) how to ins t all and configure the dk2000 developer?s kit pc board. MC2400 t e chni cal specifi cati ons v
MC2400 t e chni cal specifi cati ons vi
t able o f contents warr an ty ....................................................................................................................... ............................... iii safety notice .................................................................................................................. .............................. iii disclaimer ..................................................................................................................... ................................ iii related docu ments .............................................................................................................. ......................... v table of con t ents .............................................................................................................. .......................... vii 1 the naviga tor f a mily ......................................................................................................... ...................... 9 2 f uncti on al ch arac teristic s ................................................................................................... ................... 11 2. 1 configurations , pa ram e te rs, and pe rform a nce .............................................................................. 11 2. 2 physical cha r a c teristics and m ounting dim e nsions ....................................................................... 13 2. 2. 1 cp chi p ........................................................................................................................ ......... 13 2. 2. 2 i/o c h ip ....................................................................................................................... .......... 14 2. 3 environm ental and electrical ratings ........................................................................................... .1 5 2. 4 system confi g uration ........................................................................................................... ......... 15 2. 5 peripheral de vi ce addres s m a pping.............................................................................................. .1 6 3 electric a l char acteris t ics ................................................................................................... ..................... 17 3. 1 dc c h aract eris tic s ............................................................................................................. ............ 17 3. 2 ac c h aract eris tic s ............................................................................................................. ............ 17 4 i/o timing diagrams .......................................................................................................... .................... 19 4. 1 clock .......................................................................................................................... .................. 19 4. 2 qua d rature enc ode r i n put ....................................................................................................... ...... 19 4. 3 reset .......................................................................................................................... ................... 19 4. 4 host i n terface, 8/8 m ode ....................................................................................................... ........ 20 4. 4. 1 inst ruction wri t e, 8/8 m o de ................................................................................................... 2 0 4. 4. 2 data write, 8/8 m ode ........................................................................................................... .2 0 4. 4. 3 data rea d , 8/ 8 m o de ............................................................................................................ .. 21 4. 4. 4 status rea d , 8/ 8 m ode .......................................................................................................... .. 21 4. 5 host i n terface, 8/16 m ode ...................................................................................................... ....... 22 4. 5. 1 inst ruction wri t e, 8/16 m o de ................................................................................................. 22 4. 5. 2 data write, 8/16 m o de .......................................................................................................... .2 2 4. 5. 3 data rea d , 8/ 16 m ode ........................................................................................................... .2 3 4. 5. 4 status rea d , 8/ 16 m ode ......................................................................................................... .2 3 4. 6 host i n terface, 16/ 16 m ode ..................................................................................................... ...... 24 4. 6. 1 inst ruction wri t e, 16/16 m ode ............................................................................................... 24 4. 6. 2 data write, 16/ 1 6 m ode......................................................................................................... 24 4. 6. 3 data rea d , 16/16 m ode .......................................................................................................... 25 4. 6. 4 status rea d , 16/16 m ode ........................................................................................................ 25 4. 7 external m e m o ry tim i ng ......................................................................................................... ...... 26 4. 7. 1 external m e m o ry rea d ........................................................................................................... 26 4. 7. 2 external m e m o ry wr ite ......................................................................................................... 2 6 4. 8 peripheral de vi ce tim i ng ....................................................................................................... ........ 27 4. 8. 1 peripheral de vi ce rea d ......................................................................................................... .. 27 4. 8. 2 peripheral de vi ce write ........................................................................................................ .2 7 MC2400 t e chni cal specifi cati ons vii
5 pin o u t s and pin descrip t ions ................................................................................................. ................. 28 5. 1 pinouts fo r m c 2440 ............................................................................................................. ........ 28 5. 2 pinouts fo r m c 2420 ............................................................................................................. ........ 29 5. 3 pinouts fo r m c 2410 ............................................................................................................. ........ 30 5. 4 pin descri p tion ta bles ......................................................................................................... ........... 31 5. 4. 1 i/o c h ip ....................................................................................................................... .......... 31 5. 4. 2 cp chi p ........................................................................................................................ ......... 34 6 applicatio n notes ............................................................................................................ ......................... 37 6. 1 design ti ps .................................................................................................................... ............... 37 6. 2 isa bus in terf ace .............................................................................................................. ........... 39 6. 3 rs-232 se rial interface ........................................................................................................ ........ 41 6. 4 rs 422/ 485 se rial inte rface .................................................................................................... ...... 43 6. 5 p w m m o tor interface ............................................................................................................ ...... 45 6. 6 12-bit parallel dac interface .................................................................................................. ..... 47 6. 7 16-bit serial dac interface .................................................................................................... ...... 49 6. 8 12-bit a/d interface ........................................................................................................... ........... 51 6. 9 16-bit a/d input ............................................................................................................... ............ 53 6. 10 ram inte rface .................................................................................................................. ............ 55 6. 11 user-define d i/ o ............................................................................................................... ............ 57 MC2400 t e chni cal specifi cati ons viii
1 the na vigator f a mily mc2100 series mc2300 series MC2400 series mc2500 series mc2800 series # of axe s 4, 2, o r 1 4, 2 o r 1 4, 2 o r 1 4, 2, o r 1 4 o r 2 motor type su pported brushed servo brushless servo ste ppi n g s t e ppi n g brushed servo + bru s hl e s s se rv o output format bru s he d se rv o (single phase) commutated (6-step or sinusoidal) mi c r oste ppi ng pulse an d directio n brushed servo (single phase) + commutated (6-step si nusoidal) incremental encoder input parallel word device input p a rallel communication serial commu nication diagnostic port s-curve profiling electronic gea r ing on-the-fly changes directional li mit switche s programmabl e bit output software-invertable sig n al s pid s e rvo control - - feedforward (accel & vel) - - der i vative sa mpl i ng time - - data trace/diagnostics pwm output - motion error detection (wit h en co der) (wit h en co der) axis settled in dicator (wit h en co der) (wit h en co der) dac-comp ati b le output - pulse & direction output - - - - index & ho m e sig n al s position captu r e analog input user-defined i/o external ram support multi-chip synchronization (21x3) (23x3) (24x3) (28x3) chipset part n u mbers mc214 0 (4 axes) mc212 0 (2 axes) mc211 0 (1 axis) mc234 0 (4 axes) mc232 0 (2 axes) mc231 0 (1 axis) mc244 0 (4 axes) mc242 0 (2 axes) mc241 0 (1 axis) mc254 0 (4 axes) mc252 0 (2 axes) mc251 0 (1 axis) mc284 0 (4 axes) mc282 0 (2 axes) developer's kit p/n's: d k 2 1 0 0 d k 2 3 0 0 d k 2 4 0 0 d k 2 5 0 0 d k 2 8 0 0 MC2400 t e chni cal specifi cati ons 9
intr oduction this manu al describes the operational char acteristics of the mc2440, mc2420 and mc2410 motion proc essors fr om pmd. these devices ar e mem b ers of pm d?s seco n d -gener ati on moti on pro c e ssor family, w h ic h consis ts of 14 separ at e pr oducts org aniz e d into 5 series . eac h of thes e devices is comple te c h ip-based mo tio n p r ocess o rs. th ey pr ovide tr aj ect ory ge ne rat i on and rela ted m o ti on c o n t rol functi ons. d e pendi n g o n th e ty pe of mo t o r co nt rolled t h ey provide servo lo op cl o s ure, on- b oar d commut a ti o n for brushles s mot o rs, a n d high sp eed pu lse and directi on outpu t s. tog e th er t h ese pr oducts pr ovide a sof t war e-c omp a ti ble f a mily of dedic a ted mo tio n pro cessors t h at c an h a n dle a large v a rie t y of syste m c o n f igurati ons. eac h of t h es e chips utili ze a similar ar chi t e c ture, c onsis ti ng of a high -s peed c o m p uta t io n unit, al o n g wit h an asic ( a pp licat ion sp ecific in tegrat ed circ uit ) . th e co mput at ion uni t co nt a i ns speci al o n - bo ard hardw a r e th at m a kes it well suited f o r th e t a sk of moti on co ntr o l. along wi th si milar h a rdwar e arc h ite c tur e thes e chi p s als o shar e mos t softw a re c o m m ands, so th a t softw a re wri t t e n fo r on e c h i p set m a y be r e-used with a n o t he r, eve n t hough th e ty p e of m o t o r m a y b e different. eac h chi p se t consis ts of tw o pqfp (pl a s t ic quad fla t pack) i c s: a 1 00-pin in put/ output (i/o ) chip , and a 13 2-pin com m a n d proc essor (cp) chi p . th e five diffe rent s e ries in t h e n a vigat o r family are desi gned for a pa r t icular t y p e of mot o r or co n t rol schem e . her e is a summary descripti on of eac h series. f a mily summary mc2100 series (mc2140, mc2120, mc2110) ? th is series o u tp ut s mo to r co mman ds in eith er pwm or da c-c o m pati b le form at f o r use with brus hed servo m o t o rs, or with brush l ess servo mot o rs h a vin g exter nal c o mmuta tio n . mc2300 series (mc2340, mc2320, mc2310) ? this series outputs s i nusoidally commutated mot o r sign als ap pro p ria t e f o r driving brushless mo tors. dep e nding on the m o t o r t y pe, t h e outpu t is a two- p hase or thre e- ph ase si gnal in eit h er pwm or da c-c o m pati b le form at. MC2400 series (mc2440, mc2420, mc2410) ? this series pr ovides micros tep p in g signals for step ping mo t o rs. tw o p has ed signals pe r axis are ge ner a ted in ei th er pwm or da c-c o m pati b le form at. mc2500 series (mc2540, mc2520, mc2510) ? these chipse ts pr ov ide high-s pee d pulse and direction signals for stepping motor systems. mc2800 series (mc2840, mc2820) ? this series outputs sinusoidal l y or 6-st ep c o mmuta ted m o tor signals a ppr op riate f o r drivi n g brushl ess servo m o t o rs a s well as pw m or dac- c o mp ati b le out p uts for driving br ushed servo motors. MC2400 t e chni cal specifi cati ons 10
2 functional char acteristics 2.1 configur ations , par amete r s , and performance available config urations 4 axes (mc2440), 2 axes (mc24 20), or 1 axis (m c2410) operating mo de s open loop (moto r command is driven from output of trajectory generator & microstep generator, encoder input used for stall detection) communi cation mode s 8/8 parallel (8 bit external parallel bus with 8 bit int e rnal command word size) 8/16 parallel (8 bit external parallel bus with 16 bit internal command word size) 16/16 parallel (16 bit external parallel bus with 16 bit internal com m and word size) point to point asynchronous serial multidrop asynchronous serial serial port bau d rate range 1,200 baud to 416,667 baud position range -2,147,483,648 to +2,147,483,647 counts velocity range -32,768 to +32,7 67 counts/sample with a resolution of 1/65,536 counts/sample acceleratio n /de c eleration ra nge s -32,768 to +32,7 67 counts/sample 2 with a resolution of 1/65,536 counts/sample 2 jerk range 0 to ? counts/sa m ple 3 , with a resolution of 1/4,29 4,967,296 counts/sample 3 profile mode s s-curve point-to-point (velocity, a ccele ration, jerk, and position par ameters) trapezoidal point-to-point (velocity, acce leration, deceleration, an d position parameters) velocit y -contouring (velocity, accele ration, and deceleration parameters) electronic gear (encoder or t r ajectory position of one axis used to drive a second axis. ma ster and slave a x es and gear ratio parameters) electronic gear r a tio range -32,768 to +32,7 67 with a resolution of 1/65,536 (negative and po sitive direction) position error tracking motion error window (allows axis to be stopped upon exceeding p r ogrammable window) tracking window (allows flag to b e set if axis exce eds a programm able position window) axis settled (allo ws flag to be set if axis e xceed s a programmable position window for a pro g rammable amo unt of time after trajectory motion is compete) microsteppi ng waveform sinusoida l number of mi crosteps per full s t ep programmable 1 to 256 motor output m odes pwm (8-bit resolution at 80 khz or 10-bit resolution at 20 khz) dac (16 bits) maximum encoder rate incremental (up to 5 mcounts/se c ) parallel-word (u p to 160 mcounts/sec) parallel encoder word siz e 16 bits parallel encoder read rate 20 khz (reads all axes every 50 cycle rate timing range 153.6 minimum cycl e t i me 153.6 multi-chip synchronization <10 MC2400 t e chni cal specifi cati ons 11
limit switc h es 2 per axis: one f o r each direction of travel position-c apture triggers 2 per axis: index and home signa ls other digital sig n als (p er axi s) 1 axisin signal p e r axis, 1 axisout signal per axis software-invert able s i gnal s encoder a, encoder b, index, home, axisin, a x isout, positivel i mit, negativelimit (all individual ly programmable per axis) analog inp u t 8 10-bit analog inputs user define d dis c rete i/o 256 16-bit wide user defined i/o ram/external m e mory s u pport 65,536 blocks of 32,768 16-bit words per block. total accessib le memory is 2,147,483,648 16 bit words trace mo des one-time continuous max. nu mber of trace variabl es 4 number of trace able v a riable s 27 number of ho st instructions 116 MC2400 t e chni cal specifi cati ons 12
2.2 ph y s ical char acteristics and mounting dimensions 2.2.1 cp chip all dimensions are in inches (with millimeters in brackets). dimensio n m i n i m u m (inche s) maximu m (inche s) minimu m (m m) maximu m (m m) d 1 . 0 7 0 1 . 0 9 0 2 7 . 1 7 8 2 7 . 6 8 6 d 1 0 . 9 3 4 0 . 9 6 6 2 3 . 7 2 3 2 4 . 5 3 6 d 2 1 . 0 8 8 1 . 1 1 2 2 7 . 6 3 5 2 8 . 2 4 4 d 3 0 . 8 0 0 n o m i n a l 2 0 . 3 2 n o m i n a l MC2400 t e chni cal specifi cati ons 13
2.2.2 i/o chip all dimensions are in millim eters. dimensio n m i n i m u m (m m) nominal (m m) maximu m (m m) minimu m (inche s) nominal (inche s) maximu m (inche s) a 3 . 4 0 0 . 1 3 3 8 5 8 3 a 1 0 . 2 5 0 . 3 3 0 . 0 0 9 8 4 2 5 0 . 0 1 2 9 9 2 1 a 2 2 . 5 5 2 . 8 0 3 . 0 5 0 . 1 0 0 3 9 3 7 0 . 1 1 0 2 3 6 2 0 . 1 2 0 0 7 8 7 b 0 . 2 2 0 . 3 8 0 . 0 0 8 6 6 1 4 0 . 0 1 4 9 6 0 6 c 0 . 1 3 0 . 2 3 0 . 0 0 5 1 1 8 1 0 . 0 0 9 0 5 5 1 d 2 2 . 9 5 2 3 . 2 0 2 3 . 4 5 0 . 9 0 3 5 4 3 3 0 . 9 1 3 3 8 5 8 0 . 9 2 3 2 2 8 3 d 1 1 9 . 9 0 2 0 . 0 0 2 0 . 1 0 0 . 7 8 3 4 6 4 6 0 . 7 8 7 4 0 1 6 0 . 7 9 1 3 3 8 6 e 1 6 . 9 5 1 7 . 2 0 1 7 . 4 5 0 . 6 6 7 3 2 2 8 0 . 6 7 7 1 6 5 4 0 . 6 8 7 0 0 7 9 e 1 1 3 . 9 0 1 4 . 0 0 1 4 . 0 1 0 . 5 4 7 2 4 4 1 0 . 5 5 1 1 8 1 1 0 . 5 5 1 5 7 4 8 e 0 . 6 5 b s c 0 . 0 2 5 5 9 0 6 b s c l 0 . 7 3 0 . 8 8 1 . 0 3 0 . 0 2 8 7 4 0 2 0 . 0 3 4 6 4 5 7 0 . 0 4 0 5 5 1 2 c c c 0 . 1 0 0 . 0 0 3 9 3 7 0 t h e t a 0 7 0 0 . 2 7 5 5 9 0 6 MC2400 t e chni cal specifi cati ons 14
2.3 envir onmental and electrical r a tings all ratings and ra nges ar e for bot h t h e i/o and c p c h ips . storage tem p er ature (t s ) -55 c to 150 c operating tem p erature (t a ) 0 c to 70 c* power dissip a ti on (p d ) 600 mw (i/o an d cp combined) nominal clo c k f r equency (f clk ) 40.0 mhz supply volta g e l i mits (v cc ) -0.3v to +7.0v supply volta g e operating ran g e (v cc ) 4.75v to 5.25v * an industri a l version wi th an o p er ati n g r ange of -40 c t o 85 c is als o avail abl e. please c o n t a c t pmd for m o r e information. 2.4 sy stem conf igur ation the following figure shows the principal control and data path s in an MC2400 system. host serial-port host i/o cp host dat a0-15 ~hostslct parallel port serial port (alternatives) system clock (40 mhz) hostintrpt navigator motion processor 20mhz clock host rdy ~h o s twri te host cmd ~host r ead navigator motion processor axisout negat ive positive axisin limit switches motor amplifier a home i ndex b encoder pw m out put analog input s p a r a l l e l - w o r d i n p u t external memory other user devices 16-bit data bus d a c o u t p u t d/a converter hall sensors (mc2300 only) user i/o s e r i a l p o r t c o n f i g u r a t i o n the cp c h ip c o ntai ns the pr ofile ge ner a tor, whic h cal c ulates vel o ci ty, accele r ati o n, and position values for a tr ajec tor y ; a n d t h e c o mmu tati on uni t , whi c h cal c ulat es a mot o r c o mm a n d for e a ch m o t o r ph ase. the c o mmut a ti on u n it pr oduces o n e of two ty p e s of out p ut: ? a pulse-widt h m o dulated (p wm ) signal o u tput w h ich p a sses via th e data bus to the i/o chip , whe r e t h e outpu t sign a l gener a t o r se nds it to t h e mot o r a m plifi e rs; or MC2400 t e chni cal specifi cati ons 15
? a dac -co mp atibl e value r o uted via th e data bus to the ap pro p ria t e d / a conve r ter . axis positi on infor m a t io n r e turns t o t h e moti on pro c e ssor thr o ugh t h e i/o chi p , i n th e for m of enc o der fe edback, or thr o ug h the cp c h ip, in the for m of par allel-w o r d feedback. 2.5 p e ripher a l de vice addr ess mappi ng device addresses on t h e c p chip ?s data bus are me mor y - m ap ped t o t h e follo wing l o cati ons: a d d r e s s d e v i c e d e s c r i p t i o n 0200h serial port data contains the co nfiguration data (transmis s ion rate, pari t y, st op bi ts, etc ) fo r th e async h r o n o u s serial po rt 0 8 0 0 h p a r a l l e l - w o r d e n c o d e r base addre ss for parallel-word feedback devices 1 0 0 0 h u s e r - d e f i n e d base address for user-defined i/o devices 2000h ram page pointer page po inter to external memory 4 0 0 0 h m o t o r - o u t p u t d a c s base addre ss for motor-ou tput d/a converters 8 0 0 0 h i / o c h i p base address for i/o chip commu nications MC2400 t e chni cal specifi cati ons 16
3 electrical char acteristics 3.1 dc char acteristics (v cc and t a pe r ope rati ng r a t i ngs, f clk = 40.0 mhz) s y m b o l p a r a m e t e r minim u m maximu m con d iti o n s v cc supply voltage 4.75 v 5.25 v i dd supply current 120 ma open outputs input vol t ages v ih logic 1 input vo ltage 2.0 v v cc + 0.3 v v il logic 0 input vo ltage -0.3 v 0.8 v v ihr e s e t logic 1 voltage f o r reset pin (res et) 2.2 v v cc + 0.3 v ou tp ut v o lta g e s v oh logic 1 output voltage 2.4 v @cp i o = -23 ma @i/o i o = -6 ma v ol logic 0 output voltage 0.33 v @cp i o = 6 ma @i/o i o = 6 ma ot her i out tri-state output l eakage current -5 a 5 a @cp 0 < v out < v cc i in input current -10 a -10 a 10 a -10 a @cp @i/o 0 < v i < v cc c io input/output capacitance 15 pf 10 pf @cp typical @i/o analo g in pu t z ai analog input sou r ce impedance 9k ? e dnl differential nonlinearity error. difference between the step width and the ideal value. - 1 1 . 5 l s b e inl integral nonlinea rity error. maximum deviat i on from the best straight line through the adc transfer characteristics, e xclud in g the quantization erro r. + / - 1 . 5 l s b 3.2 a c char acteristics see timi ng diagrams, section 4, for tn numbers. the symbol ? ~ ? in dicates a c tiv e low sign al. timi ng i nterval tn m i n i m u m m a x i m u m clock frequency (f cl k ) > 0 mhz 40 mhz (n ote 1 ) clock pulse wid th t1 10 nsec clock period (note 3 ) t 2 2 5 n s e c encoder pulse width t3 150 nsec dwell time per state t4 75 nsec index setup and hold (relative to quad a and quad b low) t 5 0 n s e c MC2400 t e chni cal specifi cati ons 17
timi ng i nterval tn m i n i m u m m a x i m u m ~hostslct hold time t6 0 nsec ~hostslct setup time t7 0 nsec hostcmd setup time t8 0 nsec hostcmd hold time t9 0 nsec read data access time t10 25 nsec read data hold time t11 10 nsec ~hostread high to hi-z time t12 20 nsec hostrdy delay time t13 100 nsec 150 nsec ~hostwrite pulse width t14 70 nsec write data dela y time t15 15 nsec write data hold time t16 0 nsec read recovery time (n ote 2 ) t 1 7 6 0 n s e c wr ite recover y t i me (n ote 2 ) t 1 8 6 0 n s e c read pulse widt h t19 70 nsec address setup delay time t20 7 nsec data access time t21 19 nsec data hold time t22 2 nsec address setup delay time t23 7 nsec address setup t o writeenable high t24 72 nsec ramslct low to writeenable high t25 79 nsec address hold time t26 17 nsec writeenable pulse width t27 39 nsec data setup time t28 3 nsec data setup before write high ti me t29 42 nsec address setup delay time t30 7 nsec data access time t31 71 nsec data hold time t32 2 nsec address setup delay time t33 7 nsec address setup t o writeenable high t34 122 nsec periphslct low t o writeenable high t35 129 nsec address hold time t36 17 nsec writeenable pulse width t37 89 nsec data setup time t38 3 nsec data setup before write high ti me t39 92 nsec read to write delay time t40 50 nsec reset low pulse width t50 5.0 se c ramslct low to strobe low t51 1 nsec strobe high to ramslct high t52 4 nsec writeenable low to strobe low t53 1 nsec strobe high to writeenable high t54 3 nsec periphslct low t o strobe low t55 1 nsec strobe high to periphslct high t56 4 nsec device ready/ outputs initialize d t57 1 ms note 1 perfor ma nc e f i gures and tim i ng inf o rm ati o n valid at f clk = 40.0 mhz only. for timing infor m a t io n a n d perf orm a n ce p a ra met e rs at f clk < 40.0 mhz refer to section 6.1. note 2 for 8/8 and 8/16 interface modes only. note 3 th e clo c k low / high split ha s an all o wa ble range of 45-5 5 % . MC2400 t e chni cal specifi cati ons 18
4 i/o timing diagr ams for the values of tn , ple a se refer t o t h e t a ble in se cti on 0. 4.1 clock t1 t2 m asterclkin t1 4.2 quadr atur e e n coder input t3 t3 t4 t4 t5 (= ~q ua da * ~q uad b * ~i nde x ) t5 in d e x quad a qu a d b ~i n d e x 4.3 reset v cc i/ ocl k ~reset t5 0 t5 7 MC2400 t e chni cal specifi cati ons 19
4.4 host interface , 8/8 mode 4.4.1 instruction w r i t e, 8/8 mode t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-7 hostrdy t14 t16 t8 t9 t7 t6 4.4.2 data writ e, 8/8 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t8 t18 t6 t9 t15 t14 t13 t16 low byte t14 t16 t15 high byte see note see note MC2400 t e chni cal specifi cati ons 20
4.4.3 data read, 8/8 mode ~hostslct hostcmd hostdata0-7 hostrdy ~hostread note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t8 t17 t6 t9 t13 see note t11 t12 t10 high-z high-z high-z high byte low byte t19 see note 4.4.4 status read, 8/8 mode ~hostslct t7 t8 t11 hostcmd hostdata0-7 ~hostread t12 t10 high-z high-z t6 t9 t14 MC2400 t e chni cal specifi cati ons 21
4.5 host interface , 8/16 mode 4.5.1 instruction w r i t e, 8/16 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t6 see note t8 t18 t9 t14 t14 see note t16 t16 t15 t13 t15 low byte high byte 4.5.2 data writ e, 8/16 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t8 t6 t9 t15 see note see note low byte t16 t13 t16 t15 high byte t18 t14 t14 MC2400 t e chni cal specifi cati ons 22
4.5.3 data read, 8/16 mode hostdata0-7 ~hostslct t7 t8 t19 t6 t9 t13 t11 hostcmd hostrdy ~hostread t12 t10 high-z high-z high-z high byte low byte note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. see note see note 4.5.4 status read, 8/16 mode ~hostslct t7 t8 t17 t6 t9 t11 hostcmd hostdata0-7 ~hostread t12 t10 high-z high-z high-z high byte low byte t19 MC2400 t e chni cal specifi cati ons 23
4.6 host interface , 16/ 16 m ode 4.6.1 instruction w r i t e, 16/16 mod e t7 t6 t9 t14 t16 t8 t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-15 hostrdy 4.6.2 data writ e, 16/16 mode t7 t6 t9 t14 t16 t8 t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-15 hostrdy MC2400 t e chni cal specifi cati ons 24
4.6.3 data read, 16/16 mode ~hostslct t7 t8 t13 t11 hostcmd hostdata0-15 hostrdy ~hostread t12 t10 high-z high-z t6 t9 t19 4.6.4 status read, 16/16 mode ~hostslct t7 t8 t11 hostcmd hostdata0-15 ~hostread t12 t10 high-z high-z t6 t9 t19 MC2400 t e chni cal specifi cati ons 25
4.7 external memory timing 4.7.1 external memo ry read note: pmd r ecomme nds using mem o ry with an access time no gre a ter than 15 ns e c . ~ramslct addr0-addr15 w/~r ~writeenbl data0-data15 t21 t20 t40 ~strobe t52 t51 4.7.2 external memo ry write addr0-addr15 r/~w w/~r ~writeenbl data0-data15 ~ramslct t26 t27 t27 t23 t28 t24 t25 t29 ~strobe t53 t54 MC2400 t e chni cal specifi cati ons 26
4.8 p e ripher a l de vice timing 4.8.1 periph eral d evi ce r e ad ~periphslct addr0-addr15 w/~r ~writeenbl data0-data15 t31 t32 t30 t31 t40 ~strobe t56 t55 4.8.2 periph eral d evi ce writ e addr0-addr15 r/~w w/~r ~writeenbl data0-data15 ~periphslct t36 t37 t37 t33 t38 t34 t35 t39 ~strobe t53 t54 MC2400 t e chni cal specifi cati ons 27
5 pinouts and pin descriptions 5.1 pinouts for mc2440 i/o cp ~wri te enb l ~ p e r ip hs lc t 81 8 92 10 0 94 cp data8 cp data9 cp d a ta 1 0 cp d a ta 1 1 cp d a ta 1 2 cp d a ta 1 3 cp d a ta 1 4 cp d a ta 1 5 ho s t c m d ho s t r d y ~ h ostrea d ~ho s tw rit e ~ho s tsl c t 12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 38 36 35 32 31 37 42 39 ho s t d a t a 0 ho s t d a t a 1 ho s t d a t a 2 ho s t d a t a 3 ho s t d a t a 4 ho s t d a t a 5 ho s t d a t a 6 ho s t d a t a 7 ho s t d a t a 8 ho s t d a t a 9 ho s t d a t a 1 0 ho s t d a t a 1 1 ho s t d a t a 1 2 ho s t d a t a 1 3 ho s t d a t a 1 4 ho s t d a t a 1 5 cpda t a 0 cpda t a 1 cpda t a 2 cpda t a 3 cpda t a 4 cp data5 cp data6 cp data7 18 14 71 13 70 15 69 68 77 53 54 52 41 43 50 89 24 5 91 c p intrpt cp r / ~ w c pst ro be c pper i p h sl ct c padd r 0 c padd r 1 c p a d dr 15 cp c l k m a ste r clkin ho s t mo d e 0 ho s t mo d e 1 47 25 49 82 48 44 93 29 33 51 83 88 30 58 28 45 qu ada 1 qu adb 1 ~ i nde x1 ~hom e 1 qu ada 2 qu adb 2 ~ i nde x2 ~hom e 2 qu ada 3 qu adb 3 ~ i nde x3 ~hom e 3 qu ada 4 qu adb 4 ~ i nde x4 ~hom e 4 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 11 0 11 1 11 2 11 4 11 5 11 6 11 7 11 8 11 9 12 2 12 3 12 4 12 5 12 6 12 7 12 8 43 44 99 98 53 58 srlr cv srlx m t srle na bl e ~h os t i nt rpt i / o in tr p t i/oc l k data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 data 10 data 11 data 12 data 13 data 14 data 15 ad dr0 ad dr1 ad dr2 ad dr3 ad dr4 ad dr5 ad dr6 ad dr7 ad dr8 ad dr9 ad dr1 0 ad dr1 1 ad dr1 2 ad dr1 3 ad dr1 4 ad dr1 5 4 6 13 0 12 9 41 r/~w ~stro b e ~r am slc t ~r es et w/ ~ r 13 2 1 63 65 54 49 64 66 55 51 po sl i m 1 po sl i m 2 po sl im 3 / sy n c h po sl i m 4 negl im 1 negl im 2 negl im 3 negl im 4 85 86 87 94 95 96 97 72 10 0 10 6 67 74 89 75 88 76 83 77 82 axi s o u t 1 axi s o u t 2 axi s o u t 3 axi s o u t 4 axi s i n 1 axi s i n 2 axi s i n 3 axi s i n 4 a n al og 1 a n al og 2 a n al og 3 a n al og 4 a n al og 5 a n al og 6 a n al og 7 a n al og 8 an al og vc c an al og refhig h an al og r e f l o w an al og g n d 84 21 85 59 20 61 26 79 pw mmag 1 a p w mma g2 a p w mma g3 a p w mma g4 a p w ms i gn1 a p w ms i gn4 a p w ms i gn3 a p w ms i gn2 a 6 0 p w mma g1 b p w mma g2 b p w mma g3 b p w mma g4 b p w ms i gn1 b p w ms i gn2 b p w ms i gn3 b p w ms i gn4 b 62 87 19 78 23 86 63 80 45 nc/p o sl i m 3 vc c 16 , 17 , 4 0 , 6 5 , 6 6 , 67 , 90 gnd 4 , 9, 22 , 34 , 46 , 5 7 , 6 4 , 7 2 , 84 , 96 u n a s si gn ed 27 , 55 , 5 6 gnd 3, 8 , 1 4 , 2 0 , 2 9 , 37, 46 , 56 , 59 , 6 1 , 71, 92 , 10 4, 1 1 3 , 12 0 u n a s si gn ed 5, 3 0 - 3 4, 3 8 , 3 9 , 42, 48 , 57 , 68 - 7 0 , 7 3 , 78- 8 1 , 90, 91 , 10 1, 1 0 2 , 1 0 5 , 10 7- 1 09, 13 1 vc c 2, 7 , 1 3 , 2 1 , 3 5 , 36, 40 , 47 , 50 , 52 , 60 , 62 , 9 3 , 1 0 3 , 12 1 MC2400 t e chni cal specifi cati ons 28
5.2 pinouts for mc2420 i/o 81 8 92 10 0 94 cp da ta8 cp da ta9 cp da ta 10 cp da ta 11 cp da ta 12 cp da ta 13 cp da ta 14 cp da ta 15 ho stcm d ho strd y ~ h ostr ea d ~ho s twr i te ~ho s tsl c t 12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 38 36 35 32 31 37 42 39 ho stda ta 0 ho stda ta 1 ho stda ta 2 ho stda ta 3 ho stda ta 4 ho stda ta 5 ho stda ta 6 ho stda ta 7 ho stda ta 8 ho stda ta 9 ho stda ta 10 ho stda ta 11 ho stda ta 12 ho stda ta 13 ho stda ta 14 ho stda ta 15 cp d a ta 0 cp d a ta 1 cp d a ta 2 cp d a ta 3 cp d a ta 4 cp da ta5 cp da ta6 cp da ta7 18 14 71 13 70 15 69 68 77 53 54 52 41 43 50 89 24 5 91 cpintrpt cpr/~w cps t ro be c p peri ph sl ct cpa d d r 0 cpa d d r 1 c p a d dr 15 cpclk mas t e r cl k i n h o stmo de0 h o stmo de1 47 25 49 82 48 44 93 29 quad a 1 quad b 1 ~ i nd ex 1 ~ho m e1 quad a 2 quad b 2 ~ i nd ex 2 ~ho m e2 21 85 61 p w mma g1 a p w mmag 2 a pwm s ig n1 a pwm s ig n2 a 6 0 p w mmag 1 b p w mmag 2 b pwm s ig n1 b pwm s ig n2 b 62 87 23 86 cp ~w rit e en bl ~pe r ip hs lct gnd 3 , 8, 14 , 20 , 2 9 , 3 7 , 4 6 , 56 , 59 , 6 1 , 71 , 92 , 1 0 4 , 11 3, 1 2 0 un as si gn ed 5, 30- 3 4 , 38, 39 , 42 , 4 5 , 4 8 , 4 9 , 5 1 , 55, 57 , 67 - 7 0 , 73 , 7 8 - 8 1 , 9 0 , 91 , 96 , 97 , 1 0 1 , 10 2, 1 0 5 , 1 06- 10 9, 1 3 1 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 11 0 11 1 11 2 11 4 11 5 11 6 11 7 11 8 11 9 12 2 12 3 12 4 12 5 12 6 12 7 12 8 43 44 99 98 53 58 srl r c v srl x m t s r le na bl e ~ h os t i ntr p t i/ o i n t r p t i/ o c l k da ta 0 da ta 1 da ta 2 da ta 3 da ta 4 da ta 5 da ta 6 da ta 7 da ta 8 da ta 9 da ta 10 da ta 11 da ta 12 da ta 13 da ta 14 da ta 15 ad dr 0 ad dr 1 ad dr 2 ad dr 3 ad dr 4 ad dr 5 ad dr 6 ad dr 7 ad dr 8 ad dr 9 ad dr 1 0 ad dr 1 1 ad dr 1 2 ad dr 1 3 ad dr 1 4 ad dr 1 5 4 6 13 0 12 9 41 r/ ~w ~st r ob e ~r am sl c t ~ r es et w/~r 13 2 1 63 65 64 66 po s l i m 1 po s l i m 2 ne gl im1 ne gl im2 85 86 87 94 95 72 10 0 74 89 75 88 76 83 77 82 ax is o u t 1 ax is o u t 2 ax is i n 1 ax is i n 2 a n al og 1 a n al og 2 a n al og 3 a n al og 4 a n al og 5 a n al og 6 a n al og 7 a n al og 8 an al og v c c a n al og re fhi g h an al og ref l o w an al og g n d 84 54 nc/sy n c h vc c 1 6 , 17 , 40 , 65 , 6 6 , 6 7 , 90 gnd 4, 9, 2 2 , 34 , 46 , 57 , 6 4 , 7 2 , 8 4 , 96 u nas si gn ed 19 , 20 , 26 , 2 7 - 2 8 , 3 0 , 33 , 45 , 51 , 5 5 , 5 6 , 5 8 - 5 9 , 63 , 78 -80 , 83 , 88 vcc 2 , 7, 13 , 21 , 3 5 , 3 6 , 4 0 , 47 , 50 , 52 , 60 , 62 , 9 3 , 1 0 3 , 12 1 MC2400 t e chni cal specifi cati ons 29
5.3 pinouts for mc24 1 0 i/o 81 8 92 10 0 94 cp da t a 8 cp da t a 9 cp da ta1 0 cp da ta1 1 cp da ta1 2 cp da ta1 3 cp da ta1 4 cp da ta1 5 ho s t cmd ho s t rdy ~ h os tr ea d ~ho s tw rit e ~ho s ts lc t 12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 38 36 35 32 31 37 42 39 ho s t data 0 ho s t data 1 ho s t data 2 ho s t data 3 ho s t data 4 ho s t data 5 ho s t data 6 ho s t data 7 ho s t data 8 ho s t data 9 ho s t data 10 ho s t data 11 ho s t data 12 ho s t data 13 ho s t data 14 ho s t data 15 cp da ta0 cp da ta1 cp da ta2 cp da ta3 cp da ta4 cp da t a 5 cp da t a 6 cp da t a 7 18 14 71 13 70 15 69 68 77 53 54 52 41 43 50 89 24 5 91 c p in tr p t cp r/ ~w cp strob e cp perip h s l c t cpa ddr0 cpa ddr1 cpa ddr1 5 cp cl k mas t er c l k i n ho s t mo de 0 ho s t mo de 1 4 7 25 49 82 q u ada1 q u adb1 ~ i nd ex1 ~ h om e1 21 61 p w m m ag 1a pwm s i gn1 a p w mma g1 b pwm s i gn1 b 62 23 cp ~writ e en bl ~peri phs lct gnd 3 , 8 , 1 4 , 20 , 2 9 , 37 , 4 6 , 56 , 5 9 , 61 , 7 1 , 92 , 1 04, 11 3, 12 0 u n as si gn ed 5 , 3 0 -3 4, 38, 3 9 , 42, 45 , 48, 49 , 51, 5 5 , 57, 65 , 66, 67 -70 , 7 3 , 78 - 8 1 , 9 0 , 91 , 9 5 , 96 , 9 7 , 10 0, 10 1, 10 2, 105 , 1 0 6 - 10 9, 13 1 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 11 0 11 1 11 2 11 4 11 5 11 6 11 7 11 8 11 9 12 2 12 3 12 4 12 5 12 6 12 7 12 8 43 44 99 98 53 58 srlr c v srlxm t s r l e na bl e ~ho s tintrp t i/ o i n t rpt i/ o c l k dat a 0 dat a 1 dat a 2 dat a 3 dat a 4 dat a 5 dat a 6 dat a 7 dat a 8 dat a 9 dat a 1 0 dat a 1 1 dat a 1 2 dat a 1 3 dat a 1 4 dat a 1 5 ad dr0 ad dr1 ad dr2 ad dr3 ad dr4 ad dr5 ad dr6 ad dr7 ad dr8 ad dr9 ad dr10 ad dr11 ad dr12 ad dr13 ad dr14 ad dr15 4 6 13 0 12 9 41 r/~w ~stro b e ~r amsl ct ~res et w/ ~ r 13 2 1 63 64 po s l i m 1 ne g l i m 1 85 86 87 94 72 74 89 75 88 76 83 77 82 axi s o u t 1 ax i s in1 ana l og 1 ana l og 2 ana l og 3 ana l og 4 ana l og 5 ana l og 6 ana l og 7 ana l og 8 a n al og v c c an al og r e f h i g h ana l og ref l ow an al og gn d 84 54 nc/s y nch vc c 1 6 , 17 , 4 0 , 65 , 6 6 , 67 , 9 0 gnd 4, 9, 22 , 3 4 , 46 , 5 7 , 64 , 7 2 , 84 , 9 6 u n as si gn ed 19 , 2 0 , 26 , 2 7 -3 0, 33 , 4 4 - 4 5, 48 , 5 1 , 55 , 5 6 , 58 -60 , 6 3 , 78 -80, 83 , 85 - 8 8, 9 3 vc c 2 , 7 , 1 3 , 21 , 3 5 , 36 , 4 0 , 47 , 5 0 , 52 , 6 0 , 62 , 9 3 , 10 3, 12 1 MC2400 t e chni cal specifi cati ons 30
5.4 pin description t ables 5.4.1 i/o chip i/o chip pin n a me a nd n u mber direction description hos t c m d 8 1 input this sign al is asserted high to w r ite a hos t ins t r u ction to the m o tion processo r, o r t o read th e s t at u s of th e hostrdy and hostintrpt signals. it is asserted lo w to r e a d or writ e a data wo rd. hostrdy 8 output this sign al is u s ed to syn c hroni ze co mmunicati on betw een th e motion processo r an d the host. hostrdy will go lo w (in d ica t ing hos t p o rt bu sy) a t the en d of a r e a d or writ e op er ation a cco rding to th e in terfa c e mode in use, as follows: interface mode hostrdy goes low 8/ 8 a f te r t h e inst ru ct ion by te is tr a n sfe rr ed a f te r t h e sec o nd by te of e a c h d a ta word is tr ansfe rr ed 8/16 aft e r the secon d b y t e of the instru ction word a f te r t h e sec o nd by te of e a c h d a ta word is tr ansfe rr ed 16/16 after the 16-bit instruction wo rd aft e r ea ch 16-bit data wor d serial n/ a hostrdy will go high , in dica ting that the host p o rt is r e ady to t r ansmi t , when th e las t transmission h a s been p r ocessed. all host port communication s must b e made with hostrdy hi gh (r ea dy). a typi cal b u sy- t o-ready cycle is 12.5 microseco nds, but can b e substan t ially longer, up to 100 micro s econds. ~hos t r e a d 9 2 i n p u t w h e n ~hos tread is low , a dat a word is r e a d f r om th e mo tion processo r. ~hos t w r i t e 1 0 0 i n p u t w h e n ~hostwrite is low , a dat a word is writ ten to th e motion processo r. ~hos tslc t 9 4 i n p u t w h e n ~hostslct is low , the host port is sel e cted for r e a d ing o r writing operations. c p i n t r p t 7 7 output i/o chip to cp chip interrupt. th is sign al s e nds an int e rr upt to th e cp chip when eve r a host ? chips e t t r an smission occurs. i t sho u ld be connected to cp chip pin 53 , i/ointrpt . c p r / ~ w 5 3 input this sign al is hi gh wh en th e i / o chip is rea d i n g d a ta fro m the i / o chip , and low when i t is writing data. it shoul d b e co nnected to cp chip pin 4, r/w . c p s t r o b e 5 4 input this sign al go es lo w when th e dat a an d ad dr es s be com e vali d durin g motion pro c essor co mmunicati on with peripheral devices on the data bus, such as external memory o r a dac. it sho u ld b e connected to cp chip pin 6, strobe . cpperiphs lc t 5 2 input this sign al go es lo w when a p e ripheral device on the data bus is being addressed. i t sh ould b e c onnected to cp chip pin 130, periphs l ct. cpaddr0 cpaddr1 cpaddr15 41 43 50 i n p u t t h e s e si gnals ar e high wh en the cp chip is co mmunicating wi th the i/o chip (as distinguished from an y ot he r de vice on the data bus). t h ey should b e conn ected to cp chi p pins 110 ( addr 0 ), 111 ( addr1 ), and 128 ( addr15 ). mas t erclk i n 8 9 input this is the ma st er clock signal f o r th e motion processo r. i t is driven at a nominal 40 m h z c p c l k 2 4 output this sign al pro v ides the clo c k puls e for the cp chip. its frequen cy is half that o f m a ste r clkin (pin 89), o r 20 mhz nomin al. it is connected di rectl y to the c p chip i/ocl k signal (pin 5 8 ). MC2400 t e chni cal specifi cati ons 31
i/o chip pin n a me a nd n u mber direction description hos t mod e1 hos t mod e0 91 5 inpu t t h e s e t w o sig n a l s de te rm ine the host co mmunications mo de, as follows: hostmode1 ho stmode0 0 0 16/16 parall el (16-bit bus, 16-bit instruction) 0 1 8/8 parallel (8-bit bus, 8-bit in struction ) 1 0 8/16 parallel (8 -bit bus, 16-bit instruction) 1 1 serial hostdata0 hostdata1 hostdata2 hostdata3 hostdata4 hostdata5 hostdata6 hostdata7 hostdata8 hostdata9 hos t data10 hos t data11 hos t data12 hos t data13 hos t data14 hos t data15 12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 bi-directional, t r i -sta te thes e si gnals transmit data betwee n the host and th e mo tion processo r throu g h th e pa r a llel port . tr ans m ission is medi ated b y the con trol sign als ~hos tslc t, ~hos twrite, ~hos tre ad and h o s t cmd . in 16 bit mo de all 16 bits are used ( ho stdata0-15 ). in 8 bi t mo de only th e low-order 8 bits of data are used ( hostdata0-7 ). the hos t mode0 and hos t mod e1 signa l s sel e ct th e co mmuni cation mode this por t opera tes in. cpdata0 cpdata1 cpdata2 cpdata3 cpdata4 cpdata5 cpdata6 cpdata7 cpdata8 cpdata9 cpdata10 cpdata11 cpdata12 cpdata13 cpdata14 cpdata15 38 36 35 32 31 37 42 39 18 14 71 13 70 15 69 68 bi-dir ec t i o n a l t h e s e si gnals tr ansmit data between the i/o chip and pins data0-1 5 of the cp chip , via th e motion pro c essor da ta bu s. pwmma g1a pwmma g1b pwmma g2a pwmma g2b pwmma g3a pwmma g3b pwmma g4a pwmma g4b 21 62 85 87 20 19 79 78 output thes e pins pro v ide the puls e widt h modulat e d signal to the motor . in pwm 50 /50 m o de, this is the only signal . in pwm si gn-ma g nitude mode, this is the magn itude si gnal. the pwm reso lution is 8-bits at a fr equen c y of 80 khz, o r 1 0 -bits at 20 khz. for mc2440 all 4 pins are v a lid. fo r mc2420 only pwmmag 1 and pwmma g2 are v a lid. for mc2410 only pwmma g1 is valid. invalid or unused pins ma y be left unconn ected. pwmsig n1a pwmsig n1b pwmsig n2a pwmsig n2b pwmsig n3a pwmsig n3b pwmsig n4a pwmsig n4b 61 23 60 86 59 63 26 80 output in pwm sign- m agnit u de mode, thes e pins provide the sign (direction) of the pwm signal to th e motor amplifier. fo r mc2440 all 4 pins are vali d. for mc2420 o n ly pwmsign1 an d pwmsign2 are valid. for mc2410 only pwmsig n1 is vali d. invalid or unused pins ma y be left unconn ected. MC2400 t e chni cal specifi cati ons 32
i/o chip pin n a me a nd n u mber direction description quada1 quadb1 quada2 quadb2 quada3 quadb3 quada4 quadb4 47 25 48 44 33 51 30 58 input thes e pins pro v ide the a an d b q u a d ra tu re signals fo r th e in cr em ental enco de r fo r eac h axis . when th e a x is is movin g in th e posi t ive ( f orwa rd ) dir e ction, si gnal a leads signal b by 90. the theo re tical maxi mu m enco de r puls e rat e is 5.1 mhz . a c t u al maxi mum rate will vary, dep e n d ing on signal noise. note : man y enco ders requir e a pull-up resistor on each si gnal to est a blish a p r op er hi gh signal . check you r enc o de r?s el ec tri cal specifi ca tions. for mc2440 all 8 pins are v a lid. fo r mc2420 only th e first fo ur pins (axes 1 an d 2) are v a lid. for mc2410 only th e first two pins (axis 1 ) are valid. warning! if a valid axis pin is not used, its sig n al should be tied h i gh. invalid axis pin s may b e l e ft unconnected. ~index 1 ~index 2 ~index 3 ~index 4 49 93 83 28 input these pins pro v ide the index qua dra t ure sign als for th e incremental enco de rs . a val i d ind e x puls e i s r ecogniz ed by the chips e t when ~index , a , and b ar e all lo w . for mc2440 all 4 pins are v a lid. fo r mc2420 only ~index 1 and ~index 2 are valid. for mc2410 only ~index 1 is valid. warning! if a valid axis pin is not used, its sig n al should be tied h i gh. invalid axis pin s may b e l e ft unconnected. ~home1 ~home2 ~home3 ~home4 82 29 88 45 input these pins pro v ide the home sign als, general- purpose inputs to th e position-capture mechanism. a valid ho m e s i gnal is r e cogni z ed b y the chipse t when ~h ome n goes low . t h ese signals are sim ilar to ~in dex , but ar e not ga te d b y th e a and b en co de r channels . for mc2440 all 4 pins are v a lid. fo r mc2420 only ~home1 and ~home2 are valid. fo r mc2410 only ~home1 is valid. warning! if a valid axis pin is not used, its sig n al should be tied h i gh. invalid axis pin s may b e l e ft unconnected. vcc 16, 17, 40 , 65, 66, 67, 90 all of th ese pins must b e conn ecte d to th e i / o chip?s digi tal supply voltage, whi c h should b e in th e range 4.75 to 5.25 v. gnd 4, 9, 22, 34, 46, 57, 64, 72, 84, 96 i/o chip gro u n d . all of these pins must b e co nnected to th e digital power supply return. unas s i gn ed (mc244 0) 27, 55, 56 these pins may be l e ft un connected (floating). MC2400 t e chni cal specifi cati ons 33
5.4.2 cp chip cp chip pin n a me a nd n u mber direction description ~writeen b l 1 o u t p u t w h e n low , this signal en ables data to b e wri t t e n to th e b u s. r / ~ w 4 output this sign al is hi gh wh en th e c p chip is p e r f or ming a r e a d , an d low wh en it is perfo r ming a w r ite. i t shoul d b e connected to i/o chip pin 53, cpr/~w. ~ s t r o b e 6 output this sign al is lo w when th e dat a an d a d dr ess a r e v a lid du ring cp communication s . i t shoul d b e connected to i / o chip pin 54, cpstrobe . ~periphs lc t 1 3 0 output this sign al is lo w when peripheral devices on the da ta bus are being addressed. it should b e conn ected to i / o chip pin 52, cpperiphslct . ~ramslc t 1 2 9 output this sign al is lo w indi cat e s whe n ex te rnal memory is being accessed. ~res e t 4 1 input this is the master reset sign al. when b r ough t low , this pin res e ts th e chipse t t o its initial con d ition s . w / ~ r 1 3 2 output this sign al is the inverse of r/~ w ; it is hig h wh en r/~w is low, and vice v e rsa. for some deco de circui ts this is m o re conveni e nt than r/~w . srl r c v 4 3 input this pin receiv e s serial data from th e asyn chronous serial po rt. note ! if t h is s i gnal is n o t us ed, it should be tie d high. s r l x m t 4 4 output this pin transmits serial da ta to th e a s yn chro nous s e rial po rt . srlena b l e 9 9 outpu t this pin s e ts th e s e rial po rt enable line. sr lenable is always hig h fo r th e point- t o- point proto c ol and is hig h during transmi ssion for the mul t i-drop proto c ol. ~hos t i n t r p t 9 8 o u t p u t w h e n low , this signal caus es an interrup t to be sent to the host processo r. i / o i n t r p t 5 3 input this sign al int e rrup t s the cp chip wh en a ho s t i/o tr ansf er i s co mplet e . it should b e conn ected to i / o chip pin 77, cpintrpt . data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 b i - d i r e c t i o n a l m u l t i - p u r p o s e data lines . the s e pins comp rise the cp chip?s ext e rnal da ta b u s , used fo r all co mmuni cations with the i/o c h ip and p e riph eral devices su ch as ex te rnal me mor y or dac s . th ey ma y also be used fo r pa rallel-word inpu t an d for u s er-defined i / o operatio n s. MC2400 t e chni cal specifi cati ons 34
cp chip pin n a me a nd n u mber direction description addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr1 0 addr1 1 addr1 2 addr1 3 addr1 4 addr1 5 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 output multi-purpose address lines. these pins co m p rise the cp ch ip?s ext e rn al a d dr ess bus, us ed to sel e ct devices for communication over the data b u s. addr0 , addr1 , throu g h addr15 are conn ected to the co rrespon ding cpaddr pin s on th e i / o chip, and ar e us ed to communi c at e between the c p an d i / o chip s. other address pins may b e used for dac ou tput , pa rallel w o rd inp u t, or us er- defin e d i / o op erations. see th e navigator mo tion processor u ser? s guide for a c o m p let e me mor y m a p. i / o c l k 5 8 input this is the cp chip clo c k sign al. it shoul d b e connected to i / o chip pin 24, cpclk . anal ogvc c 8 4 input cp chip analog power supply v o ltage. this pin must b e connected to the anal og input suppl y vo ltage, whi c h must b e in th e ran g e 4 . 5-5.5 v if th e analo g in put circuitry i s not us ed, this p i n may be left unconnected. anal ogrefhi g h 8 5 input cp chip analog high voltage refere nce fo r a / d input. th e allo wed ran g e i s anal ogref low to anal ogvc c . if th e analo g in put circuitry i s not us ed, this p i n may be left unconnected. anal ogref l o w 8 6 input cp chip analog low voltage refere nce fo r a / d input. th e allo wed ran g e i s anal oggnd to anal ogrefhi gh . if th e analo g in put circuitry i s not us ed, this p i n may be left unconnected. anal o g g n d 8 7 cp chip analog input groun d . this pin must be conn ected to the analog input power supply return. if th e analo g in put circuitry i s not us ed, this p i n may be left unconnected. anal og1 anal og2 anal og3 anal og4 anal og5 anal og6 anal og7 anal og8 74 89 75 88 76 83 77 82 input these si gnals p r ovide general- purpose analo g voltage lev e ls which are samp led by an in ternal a/d conv erter. the a / d resolution is 10 bi ts. the allowed range is analogr ef low to analogr ef high . poslim1 poslim2 poslim3 poslim4 63 65 54 49 input these si gnals p r ovide inputs from th e positiv e-side (fo r ward) trav e l limit switch es. on p o wer-up o r re s e t these sign als def a ult to active lo w int e rp reta t i on, but the in terpr e tation can b e s e t e x plicitl y usin g th e setsign al sense instructi on. for mc2440 all 4 pins are v a lid. fo r mc2420 only pos l im1 and pos l im2 are valid. for mc2410 o n ly pos l im1 is valid. warning! if a valid axis pin is not u s ed, its signa l should be tied high. poslim2 is an ou tput dur in g device reset and as such any connection to gnd or v cc must be v i a a series resis t or. invalid axis pin s may al so be left un connected. MC2400 t e chni cal specifi cati ons 35
cp chip pin n a me a nd n u mber direction description poslim3/ sy nc h 54 input/o u tput on the mc2440 chipset, this p i n is the positiv e-side (forward) travel limit sw itch for axis#3. on the mc2420 and mc2410 chipsets this pin is not used. on the m c 24x3 chipset, this p i n is the synch r onization signal . in the di sabled mode, th e pin i s configured as an input an d is not us e d . in th e m a st er mo de , the pin outputs a synchronization pulse that can b e used b y slav e nodes or o t her devi ces to syn c hronize with th e int e rnal chip cy cle of th e ma ste r no de . in t h e slave mod e , th e pin is con f igu r ed as an input and a pulse on the pin synch r o n izes the in te rnal chip cy cle . warn in g! if a valid a x is limit pin is n o t use d , its sig n al sh ould be tied h i gh. n c / p o s l i m 3 4 5 input on the m c 24x0 chipset, this p i n is not used. on the mc2443 chipset, this p i n is the posit iv e-side (forward) travel limit sw itch for axis#3. on the mc2423 and mc2413 chipsets this pin is not used. warn in g! if a valid a x is limit pin is n o t use d , its sig n al sh ould be tied h i gh. negli m1 negli m2 negli m3 negli m4 64 66 55 51 input these si gnals p r ovide inputs fr om th e n e ga tive-side (r ever se) trav e l limit switch es. on p o wer-up o r re s e t these sign als def a ult to active lo w int e rp reta t i on, but the in terpr e tation can b e s e t explicitl y usin g th e setsign al sense instructi on. for mc2440 all 4 pins are v a lid. fo r mc2420 only neglim1 and neglim2 are valid. for mc2410 o n ly neglim1 is v a lid. warning! if a valid axis pin is not u s ed, its signa l should be tied high. neglim1 is an ou tput dur ing d e vice reset a nd as suc h any connection to gnd or v cc must be v i a a series resis t or. invalid axis pin s may al so be left un connected. axisout1 axisout2 axisout3 axisout4 94 95 96 97 output each of these p i ns can be con d itioned to tra ck the st at e of an y bit in th e st at us regis t ers asso ciated with its axi s . for mc2440 all 4 pins are v a lid. fo r mc2420 only axisout1 and axi s out2 ar e valid. for mc2410 only axisout1 is valid. invalid or unused pins ma y be left unconn ected. ax is in1 ax is in2 ax is in3 ax is in4 72 100 106 67 i n p u t t h e s e are general-pur pose pro g rammable inputs. t h ey m a y be used as a breakpoint input, to stop a motion axis , o r to ca use an up d a te to o c cur . for mc2440 all 4 pins are v a lid. fo r mc2420 only axisin1 an d axisin2 ar e vali d. for mc2410 o n ly axisin1 is val i d. invalid or unused pins ma y be left unconn ected. v cc 2, 7, 13, 21, 35, 36, 40, 47, 50, 52 , 60, 62, 93, 103, 121 cp di gital suppl y voltage. all of these pins must be conn ected to th e supply voltage. v cc must b e in th e ran g e 4 . 75 - 5.25 v warning! pin 35 must be tied high with a p u ll-up resistor. a nominal value of 22k ohms is suggested. gnd 3, 8, 14, 20, 29, 37, 46, 56, 59, 61 , 71, 92, 104, 113, 120 cp ground. all of these pins must b e connected to th e power supply return . unas s i gn ed 45, 48, 49 , 51, 55, 73, 90, 91, 105, 106, 107, 108, 109 thes e si gnals may be conn ec t e d to gn d fo r better noise im munity and reduce d power consumption or they can be l e ft uncon n ec te d (floating ) . unas s i gn ed (mc244 0) 5, 30-34, 38, 39, 42, 57, 68-70, 78-81, 101, 102, 131 thes e si gnals may be lef t un c onnect e d ( f loati n g). MC2400 t e chni cal specifi cati ons 36
6 application notes 6.1 design tips th e foll owing are rec o m m e n dati ons f o r t h e design of c i rcuits th at uti lize a pm d m o ti on pr ocess o r. serial i n terface th e serial i n te rface is a co nv enie nt i n te rfa c e th at c an be used befor e h o st sof t wa re h a s bee n wri tte n to c o mmu nic a te t h roug h t h e parall e l in terf ace. it is re co mme nded th a t even if th e serial in terf ac e is not utilized as a stand ard communicati on interface, that the serial recei ve and transm i t signals are broug h t t o t e st poi nts so th a t th ey m a y b e con n e c ted dur i ng initi a l b oar d configur ati o n/debugging. this is especi ally important during the prototype phase. the se rial receive line s houl d include a pu ll- up resistor to avoid spuriou s interru pts w h en i t is no t c o n n ec ted t o a tra n sceive r. if the seri al configuration decode logi c is not im plem ented (see sec t ion 6.3) and the serial interf ac e may be used for debuggi ng as men t io ned ab ove, t h e c p data bus sh o u ld be tied hig h . this pla ces the serial interface in a default configurat ion of 9600,n,8,1 after power on or reset. controlling pw m output during reset whe n t h e m o tio n pr ocess o r is in a reset st ate (wh e n t h e reset lin e is he ld low) or im mediat ely af te r a pow er o n , t h e pwm output s can b e in a n unkno w n st at e, causing u n desirabl e mo to r movem e n t . it is reco mme nded tha t t h e e n a b l e line o f an y mot o r a m plifi e r be held in a disabled stat e by t h e h o st pro cessor or s o me l o gic cir c uitry until c o mmunic a ti on to t h e m o ti on proc essor is e s tablis hed. this can be in th e f o rm o f a dela y circuit o n t h e amplifi e r e n a b le lin e aft e r p o wer up, or t h e en able li ne c an be an ded wi th t h e c p rese t line. reducin g noise and po wer co nsumpti on to r e duce t h e emission of e l ectri cal n o ise and reduce po wer co nsump t ion ( c aused b y floati n g in put s ), all unused inp u t signals c an be ti ed thr o ug h a resist or t o vcc or dire ctl y to g nd. the foll owi n g cp pins can be tied if not used: 45, 48, 68- 70, 73, 90, 91, 10 1, 102, 105, 1 07-109, 78-81. parallel word e n coder input when using parallel w o rd input for motor positi on, i t is useful to also decode t h is in form ati on i n t o the user i/o spac e. this al lows th e curre nt in put value to b e read using the chip instructi on readio for diagn o sti c purp oses. using a no n sta ndard syste m cl ock freq uenc y it is ofte n desi rable to s har e a co mmo n cl o c k amo n g sev e ral c o m p o n e n ts in a design . in the case of the pm d m o t i on pr ocess o r s it is possible to use a cl ock below th e sta n dard value o f 40m hz. in this case all sys t em frequencies will be reduced as a fraction of the i nput clock verses the standard 40mhz clock. the list bel o w shows the affected syste m parame t ers:- MC2400 t e chni cal specifi cati ons 37
? serial baud rate ? pwm carrie r f r equenc y ? timi ng ch ara c teristi c s as sh own i n secti o n 3.2 ? cycl e time ? co mmut at ion ra t e for example, if an input cl ock of 34mhz is used with a serial baud rate of 9600 th e following timing changes will result:- ? serial baud rate decreases to 9600 bps *34/40 = 8160 b p s ? pwm frequency decreases to 80 khz *34/40 = 17 khz ? cycle time per axis increases to 102.4 sec *40/34 = 12 0.47 s ec ? co mmut at ion ra t e decrea ses to 80khz *34/40 = 17 khz MC2400 t e chni cal specifi cati ons 38
6.2 is a bus inte rface a com p le te, r e ady- to-use is a (pc/a t ) bus interf ace ci rcuit h a s be en provided to il lustrate navig a to r host i n t e rfa c i n g, as well as t o make i t easi er for t h e cust omer to build a navig a t o r develo pme n t system. the interf ace betwee n the p m d navigator chips e t a n d t h e isa (pc - a t ) bus is sho w n o n th e followi ng pag e . comments on schema tic this interface uses a cpld and two 74ls245s to buffer the data lines. this interface assumes a base address is assigned in the ad dress space of a9 -a0, 300-400 hex. thes e addresses are generally availa ble f o r p r ot oty p i n g an d othe r syste m -spe cific use s withou t int e rfering wi th sy stem assig n m e nts. this in ter f ac e occu pies 16 a ddresses from xx0 to xxf hex t houg h it does no t use all th e addresses. four select lines are provided allowing the base a ddress to be set from 300 to 3f0 hex for the select lines sw1-sw 4 equal to 0- f resp ectively. t h e addre ss assignments used are as follows, where badr is the base address, 340 hex for example: a d d r e s s u s e 3 4 0 h r e a d - w r i t e d a t a 342h write co mman d -read status 344h write co mman d -read status 348h write reset [d ata = don't care] the bas e address (badr) is decoded in the 74ls688. it is combined with sa1, sa2, and sa3, (badr+0,2,4 ) to form hs eln to s e lect the i/ o chip and the 245?s. (badr+2,4 ) asserts hcmd. two addresse s are used to be c o m pati b le with t h e firs t gener a ti on pr oducts, whi c h used badr +2 to write c o m m a n d and bad r +4 to re ad sta t us. b + 8 an d iow* generat e a reset p u lse, -r s, fo r th e c p chip. the re set instru cti o n is or'd with rese t o n th e bus to i n itial i ze th e pm d chips e t w h e n the p c is reset . MC2400 t e chni cal specifi cati ons 39
MC2400 t e chni cal specifi cati ons 40
6.3 rs-232 seri al interface the interface between the navigator chipset and an rs-232 serial port is shown in the following figure. comments on schema tic s1 and s2 enc o de th e ch ar a c teris t ics of th e serial p o rt s u ch as b a ud rate, numb er o f stop bits, pa rity, etc. the cp will read these switches during initi a lizati o n, but thes e param e ters may also be set or changed using the setserialport chipse t c o mm and. th e db9 c o n n e c t or wir e d as show n ca n b e con n e c ted dir ectly to the s e rial po rt o f a pc wit hout r e quiring a null modem c abl e. MC2400 t e chni cal specifi cati ons 41
MC2400 t e chni cal specifi cati ons 42
6.4 rs 422/485 serial interface the interface between the navigator chipset and an rs-422/485 serial port is shown in the following figure. comments on schema tic use the i n cluded tabl e to de termine the jumper se tup t h at m a tc hes t h e ch osen co nf iguratio n. if using rs485, the last cp mu st have its jumpers se t to rs485 last. the db9 connector wiring is for ex ampl e o n ly. the d b 9 should be wir e d acc o rding t o th e spe c ific a t io n th at acc o mpa n ies t h e co nn ecto r to wh ich it is a tta ched. for c o rre ct o p er atio n, lo gic should be pr ovided tha t c o ntai ns t h e st ar t up serial c o n f igurati on f o r the chips e t. refer to the rs232 serial interface schematic for an example of the required logic. note that the rs485 interface cannot be used in point to point mode. it can only be used in a multi- drop c onfigur atio n w h ere t h e c h ip srle n able li ne is use d to co ntr o l tr ansmi t/rec e ive op era t io n of the serial tr ansc e i v er. chi p s in a mu lti-drop environm ent sh ould not be operated at different baud rates. this will resu lt in com m unic ati o n pr oble m s. MC2400 t e chni cal specifi cati ons 43
MC2400 t e chni cal specifi cati ons 44
6.5 pwm motor interface the following schematic shows a typical interfac e circuit between the mc2440 and an amplifier that acc e p t s an an a l og curre nt c o mma nd and a separ at e sign bit. comments on schema tic the a3952 from allegro m i crosys tems is an integrated h- bridge pack age with internal cu rrent loop contr o l whic h provides all ttl and pow er -level cir c uitry to for m a c o mple te a m plifi e r-o n - a -c hip. the only othe r com p one n ts needed ar e capaci t ors and r e sistors. th e an alo g cu rren t co mm an d input t o th e amplifi e r c h ip is constru c te d by low p a ss filteri n g th e digital magnitude output signal fr om the chipset. the sign bit is connected directly from the mc2440 chips e t to the amplifi e r. th e am plifier perf orms t h e curren t co nt r o l by c o ntinu o usly co mp ari n g th e a nal og input sig nal fr om the chi p set (c urrent com m and) to the me asured cu rren t and tuni ng o n or o ff t h e h - bridge driver s acc o rdingly to main tai n th e actu al curre nt close to the d e sired curre nt. some o f th e r e sistor and ca paci t or v a lues for t h e cir c uit may need to be adjusted depending on the par ticular v a lues for the m o tor resistance and induct anc e . in par ticular the v a lue shown for r7 (.1 75 ohm ) ma y ch ange if a maxi mum curre nt of less th an 2 amps is desired. oth e r valu es whic h ma y be adjusted are r1 and c1. the s e adjust the overall pwm fr equenc y (o ff-t i me durati on ) as well as t h e bla n king in ter v al. see t h e al legro a ppli c a t i on n o t e s for more i n fo rma t io n. MC2400 t e chni cal specifi cati ons 45
MC2400 t e chni cal specifi cati ons 46
6.6 12-bit p a r a llel d a c interface the interface between the mc2440 chip set and 2 quad 12 bit dac?s is shown in the following figure. comments on schema tic th e 12 data bi ts are wri tte n to t h e da c a ddressed by a ddress bits a0 and a1 in qu ad dac 1, w h en a2 is 0. the 12 data bits are written to the da c addressed by address bits a0 and a1 in quad dac 2, when a2 is 1. in this fas h ion cp addre sses 4000,4002 ,4004,and 4006 are used for axis 1-4, phas e a, and 4001,4003, 4005, and 4007, are used for axis 1-4 phas e b. MC2400 t e chni cal specifi cati ons 47
MC2400 t e chni cal specifi cati ons 48
6.7 16-bit serial d a c interface the following schematic shows an interface circuit between the mc2440 and a dual 16-bit serial dac. comments on schema tic the 16 data bits from the cp chip are latched in the two 74h165 shif t registers when the cp writes to address 40 0x hex, and the address bits a1 and a2 are latched in the 2 dlat latches and decoded by the 138 cp u cycle. the fed-back and-or gate la tches , the decoded wrf, and the next cl ock wi ll clear the 1 st sequencer fl op dff3. this will disable th e wrf latch and the second clock will clear the second d ff3 flop, forcing dacwrn low, an d setting the first flop since w r f will have g o ne high. da cw rn low will clear the 74109, shftcntn . the 4 bit counter, 74161, is also parallel loaded to 0, and the counter is enabled by enp go i n g high. the counter will not start counting nor the s h ift re gist er star t shif tin g until th e cl o c k aft e r t h e d a cwr n flo p sets since the load override s the count enable. w h en the dacw r flop is set the shi f t register will start s h ifti ng and the counter will count the shifts. after 1 5 shifts cn t1 5 from th e counter will g o high and the next clock will set the dacla t flop and set the shf t cn tn fl op. thi s will stop the shift after 16 shifts and assert l1 throug h l 4 dependin g o n th e address stored in the latch. the 16th clock also was counted causing the counter to roll over to 0 and cnt15 to go l o w. the ne xt cl ock will therefore cl ear the dacla t flo p causing th e dac la tc h signal l1 t h roug h l4 to t e rmi nat e a n d th e 16 bits of da ta to b e latched in the addressed dac. t h e control logic is now back i n its or iginal state waiti n g for the nex t writ e to th e dacs b y th e cp. serck is a 10mhz clock, the 20mhz cp clock divided by 2, since the a d 1866 dacs will not run at 20m hz. MC2400 t e chni cal specifi cati ons 49
MC2400 t e chni cal specifi cati ons 50
6.8 12-bit a/d interface th e foll owing schem a ti c sh ows a t y pic a l i n ter f ac e cir c uit be twe e n t h e naviga tor chi p set and a qua d 12 bit 2?s com p lem e n t a/d conv erte r used as a positi o n input devic e . comments on schema tic th e a/d co n v erter s a mpl e s all 4 axes and sequentiall y c onve r ts a n d stores t h e 2?s c o mple men t digital words. the data is read out sequentially, ax is 1 to 4. dacrd- is used to perform the read and is also used to load the counter to ffh. the counter will be rel oad ed for each read and will not count significantl y betw een reads. the counter will therefore start counting do wn after the l a st read and will generate the cvt- pulse after 12.75 s ec. the conversions will take approxi m a tel y 35 sec, and the data will be av ailable for the next set of reads after 50 sec. the 12 bit words from the a/d are extended to 16 bits with the 74ls244. MC2400 t e chni cal specifi cati ons 51
MC2400 t e chni cal specifi cati ons 52
6.9 16-bit a/d input the interf ace betwee n the navigator chi p set and 16 bi t a/d co nver ters as p a rall el input p o siti o n devices is shown in the foll owing figure. comments on schema tic th e sch e ma ti c shows a 16 bit a/d used to pr ovide p a r a llel p o siti on i nput to axis 1 and axis 2. the expansion to the remaining two axes is eas ily implemented. the 374 registers are required on the outpu t of t h e a/d conv ert e rs to mak e t h e 68-na nose c o n d acc e ss tim e of t h e cp . th e wors t-c a s e timing of t h e a/d?s specif y 83 nan osec o n ds for dat a o n th e bus a n d 83 nan osec on ds from data t o tri-state on the bus. each time the data is read the 169 counter is set to 703 decimal. this provid es a 35.2-micr osec ond delay bef o re t h e next c onve r sion . w i th a 10- micr o s eco nd co nve r sion ti me t h e data will be av ailabl e for the next set of reads afte r 50 mi croseconds. the delay is u s ed to provide a positi on s a m p le close to t h e actual posi t io n. MC2400 t e chni cal specifi cati ons 53
MC2400 t e chni cal specifi cati ons 54
6.10 ram interface th e foll owing schem a ti c sh ows an i n t e rfa ce circui t be tween the nav i gator chi p se t and external r a m. comments on schema tic the cp is capable of directl y addressing 3 2 k words of 16-bit m e m o ry. it will also use a 16 bit pagi n g regist e r to address up to 32 k wor d pages. the schem a ti c sh o w s the pagi n g and addressin g for 128kb ram chips, i.e. 4 pages per ram chip. th e page address decoding is shown for only 6 of the 16 p o ssibl e pagi n g bi ts. th e decodi ng time fr om w/ r and ds- to the mem o ry o u tput must no t exceed 18 ns. for a re ad with no w a it s t ates. the write s provide 25 e x tra ns acc e ss time f o r w/r and ds- to r e vers e the cp data bus. MC2400 t e chni cal specifi cati ons 55
MC2400 t e chni cal specifi cati ons 56
6.11 user-defined i/o th e int e rf ace bet w ee n t h e naviga tor chi p set and 16 bi ts of user out p ut a n d 16 bit s of user inpu t is show n in t h e followi ng figu re. comments on schema tic the schematic implements 1 word of user outpu t registered in the 74 ls377?s and 1 word of user inputs read via the 244?s. the schematic decodes the low 3 bits of the address to 8 possible uio addresses uio0 thr o ugh u i o7. registe r s and buffers are sh own f o r only uio0, b u t the imple m entation shown m a y be e a sily extended. th e lower 8 address bits ma y be decoded to provide up to 256 user output words and 256 user input words of 16 bits. MC2400 t e chni cal specifi cati ons 57
MC2400 t e chni cal specifi cati ons 58
for additional information, or for technical assistance, please contact pmd at (781) 674-9860. you can also e-mail your requ est to ?sup port@pm d corp.com?. visit our website at http://www.pmdcorp.com/. MC2400 t e chni cal specifi cati ons 59

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